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FUJITSU SEMICONDUCTOR DATA SHEET DS04-28203-4E ASSP BIPOLAR Image Processing A/D Converter MB40568 s DESCRIPTION (1-channel, 8-bit low-power model with built-in clamp circuit) The MB40568 is an all-parallel (flash type) A/D converter for 8-bit video applications, and uses high-speed bipolar process technology for low-power consumption and high-speed conversion. This A/D converter is capable of converting analog signals into digital signals at a rate of DC to 20 MSPS (megasamples per second). Additional circuitry including a clamp circuit and reference voltage generator circuits are build in, to make the MB40568 ideally suited for video signal processing. s FEATURES Resolution: 8 bits Linearity error: 0.15 % typ. Maximum conversion rate: 20 MSPS min. Analog input voltage: 0 to 3 V in 2 VP-P (clamp circuit) 3 to 5 V (without clamp circuit) * Digital input/output level: TTL Levels * Power supply voltage: +5 V single power supply * Power dissipation: 200 mW typ. * * * * s PACKAGES 22-pin Plastic SK-DIP 24-pin Plastic SOP (DIP-22P-M04) (FPT-24P-M02) MB40568 s PIN ASSIGNMENTS (Top view) D.GND D8 (LSB) D7 D6 D5 D4 D3 D2 D1 (MSB) CLK D.GND 1 2 3 4 5 6 7 8 9 10 11 (DIP-22P-M04) 22 21 20 19 18 17 16 15 14 13 12 A.GND VCCD VCCA VRB VINA VCLMP VOUTC VINC VCCA VCCD A.GND D.GND D8 (LSB) D7 D6 D5 D4 D3 D2 D1 (MSB) CLK D.GND A.GND 1 2 3 4 5 6 7 8 9 10 11 12 (FPT-24P-M02) (Top view) 24 23 22 21 20 19 18 17 16 15 14 13 A.GND VCCD VCCA VRB VREF VRM VINA VCLMP VOUTC VINC VCCA VCCD s PIN DESCRIPTIONS Pin no. DIP 1, 11 2 to 9 10 12, 22 13, 21 SOP 1, 11 2 to 9 10 12, 24 13, 23 Symbol D.GND D8 to D1 CLK A.GND VCCD Function Ground pin Should be connected to the analog system ground. Digital signal output pin Clock input pin Ground pin Should be connected to the analog system ground. Power supply voltage input pin Also functions as VCCA power supply, and should be in the same voltage level as VCCA pin. Power supply voltage input pin Also functions as VCCD power supply, and should be in the same voltage level as VCCD pin. Clamp circuit input pin The clamp circuit is a diode-clamp type sync chip clamp circuit. Should be shorted to ground if the clamp circuit is not used. Clamp circuit output pin A capacitor of at least 1 F should be connected between this pin and the VCLMP pin. Should be left open if the clamp circuit is not used. 14, 20 14, 22 VCCA 15 15 VINC 16 16 VOUTC (Continued) 2 MB40568 (Continued) Pin no. DIP 17 SOP 17 Symbol VCLMP Function Clamp voltage output pin A capacitor of at least 1 F should be connected between this pin and the VOUTC pin. Should be left open if the clamp circuit is not used. Analog signal input pin Analog reference voltage pin In the DIP model, this pin is internally connected to the reference circuit. Always be sure that a capacitor is connected immediately next to the IC, between this pin and the ground. The capacitor must be at least 1 F with excellent frequency characteristics. Reference voltage monitor pin Set to the midpoint of resistance between VCCA and VRB. Should be left open in normal use. Reference voltage output pin Should be left open when no reference voltage source is used. Analog reference voltage input pin When an internal reference voltage source is used, this pin should be shorted to the VREF pin. In this case, always be sure that a capacitor is connected immediately next to the IC, between this pin and the ground. The capacitor must be at least 1 F with excellent frequency characteristics. When an external reference voltage source is used, this pin will carry a current of up to 8.5 mA, therefore it is necessary to use a voltage source with sufficient sync capacity. A capacitor connection should also be used similar to that used with internal reference voltage sources. 18 19 18 -- VINA VRB -- 19 VRM -- -- 20 21 VREF VRB 3 MB40568 s BLOCK DIAGRAMS 1. SK-DIP 13 CLK 10 VINA VCCA VCCA 18 14 20 21 V CCD V CCD R1 1 R R 127 R/2 R/2 128 255 to 8 Encoder Latch & Buffer 2 9 8 7 6 5 4 3 2 D1 (MSB) D2 D3 D4 D5 D6 D7 D8 (LSB) R R R2 VRB 19 254 255 1 11 D.GND D.GND 0.6 x VCC 12 VINC VOUTC VCLMP 15 22 A.GND A.GND 16 Clamp Circuit 0.6 x VCC + 200 mV Reference 17 4 MB40568 2. SOP 13 CLK 10 VINA VCCA VCCA 18 14 22 23 VCCD VCCD R1 1 R R 127 R/2 255 to 8 Encoder 128 Latch & Buffer 2 9 8 7 6 5 4 3 2 VRM 19 R/2 D1 (MSB) D2 D3 D4 D5 D6 D7 D8 (LSB) R R R2 VRB VREF 21 20 254 255 1 11 D.GND D.GND 1 12 24 A.GND A.GND 0.6 x VCC VINC VOUTC VCLMP 15 16 Clamp Circuit 0.6 x VCC + 200 mV Reference 17 5 MB40568 s ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Power supply voltage Digital input voltage Analog input voltage Analog reference voltage* Clamp circuit input voltage Storage temperature * : Package : SOP VCCA = 2.0 0.1 V, VRB = 2.0 0.1 V WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VCCA, VCCD VIND VINA VRB VINC Tstg Rating -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -55 to +125 Unit V V V V V C s RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage*1 Analog input voltage Analog reference voltage*2 Clamp circuit input voltage* Clamp capacitance Digital high-level output voltage Digital low-level output voltage Clock pulse width at high-level Clock pulse width at low-level Operating temperature 3 Symbol VCCA, VCCD VINA VRB VINC CCLMP IOH IOL tW + Value Min. 4.75 VRB 2.75 0 1 -400 -- 22.5 22.5 0 Typ. 5.00 -- 3 -- -- -- -- -- -- -- Max. 5.25 VCCA 3.25 3 -- -- 1.6 -- -- 70 Unit V V V V F A mA ns ns C tW- Top *1: VCCA and VCCD must be used in the same voltage level. *2: Package : SOP VCCA = 2.0 0.1 V, VRB = 2.0 0.1 V *3: VINC must have an amplitude of VCCA - VCLMP . 6 MB40568 s ELECTRIC CHARACTERISTICS 1. DC Characteristics (1) Analog DC Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0C to +70C) Parameter Resolution Linearity error* Equivalent analog input resistance Analog input capacitance Analog high-level input current Analog low-level input current Clamp circuit input current Symbol -- LE RINA CINA IIHA IILA IINC VRB Reference voltage VREF Clamp voltage Reference current * : VCCA = VCCD = 5.00 V, Ta = +25C (2) Digital DC Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0C to +70C) Parameter Digital high-level output voltage Digital low-level output voltage Digital high-level input voltage Digital low-level input voltage Maximum input current High-level input current Digital low-level input current Power supply current * : VCCA = VCCD = 5.00 V, Ta = +25C Symbol VOH VOL VIHD VILD IID IIHD IILD ICC Value Min. 2.7 -- 2.0 -- -- -- -100 -- Typ. -- -- -- -- -- 0 -10 40* Max. -- 0.4 -- 0.8 100 20 -- 85 Unit V V V V A A A mA VID = 7 V VIHD = 2.7 V VILD = 0.4 V Remarks IOH = -400 A IOL = 1.6 mA VCLMP IRB 0.6 x VCC -0.1 0.6 x VCC 0.6 x VCC +0.1 V Value Min. -- -- 300 -- -- -- -600 Typ. -- 0.15 -- 40 -- -- -200 Max. 8 0.3 -- 50 45 40 -- Unit bits % k pF A A A DC Accuracy RINA = VCCA - VRB IIHA - IILA Remarks fINA = 1MHz VINA = VCCA VINA = VRB VINC = 0 V SK-DIP22P package SOP24P package Short between VREF and VRB SOP24P package -- -8.5 VRB + 0.2 -5.5 -- -3.0 V mA 7 MB40568 2. Switching Characteristics (VCCA = VCCD = 4.75 to 5.25 V, Ta = 0C to +70C) Parameter Maximum conversion rate Digital output delay time Symbol fS tpd Value Min. 20 8 Typ. -- 15 Max. -- 30 Unit MSPS ns s TIMING DIAGRAM tW + 3V tW - CLK 0V SAMPLEN SAMPLEN + 1 SAMPLEN + 2 1.5 V VINA tpd VOH D1 to D8 VOL DATAN - 1 DATAN 1.5 V DATAN + 1 8 MB40568 s TYPICAL CHARACTERISTIC CURVES Power supply current vs. Temperature 100 70 Maximum conversion rate vs. Temperature 80 Maximum conversion rate (MHz) Power supply current ICC (mA) 60 VCC = 5.00 V 60 VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V 50 40 40 20 30 10 -25 0 25 50 75 Ambient temperature Ta (C) Reference voltage vs. Temperature 100 20 -25 0 25 50 75 Ambient temperature Ta (C) Reference current vs. Temperature 100 3.20 10 VCC = 5.00 V VRB = 3.00 V Reference current IRB (mA) 8 Reference voltage VREF (V) 3.10 VCC = 5.00 V VREF--VRB Short 3.00 6 2.90 4 2.80 2 2.70 -25 0 25 50 75 Ambient temperature Ta (C) 100 0 -25 0 25 50 75 Ambient temperature Ta (C) 100 (Continued) 9 MB40568 (Continued) Digital high-level output voltage vs. Temperature 5.0 0.5 Digital low-level output voltage vs. Temperature Digital high-level output voltage VOH (V) 4.0 Digital low-level output voltage VOL (V) 0.4 3.0 0.3 2.0 VCC = 4.75 V IOH = -400 A 0.2 VCC = 4.75 V IOL = 1.6 mA 1.0 0.1 0 -25 0 25 50 75 Ambient temperature Ta (C) Clamp voltage vs. Temperature 100 0 -25 0 25 50 75 Ambient temperature Ta (C) Linerity error vs. Temperature 100 3.40 0.4 3.30 VCC = 5.00 V VCC = 5.00 V Clamp voltage VCLMP (V) Linearity error LE (%) 0.2 +LE 3.20 0 -LE -0.2 3.10 3.00 -0.4 2.90 -25 0 25 50 75 Ambient temperature Ta (C) 100 -25 0 25 50 75 Ambient temperature Ta (C) Clock pulse width vs. Power supply voltage 10 Ta = +25C 100 Digital output delay time vs. Power supply voltage 50 Digital output delay time tpd (ns) Clock pulse width tW (ns) 40 8 30 6 tW - 4 tW + 20 tPHL tPLH 10 2 0 4.50 4.75 5.0 5.25 Power supply voltage VCC (V) 5.50 0 4.50 4.75 5.0 5.25 Power supply voltage VCC (V) 5.50 (Continued) 10 MB40568 (Continued) Digital output delay time vs. Temperature 50 10 Clock pulse width vs. Temperature Digital output delay time tpd (ns) 40 VCC = 5.00 V Clock pulse width tW (ns) 8 VCC = 5.00 V 30 6 tW - tW + 20 tPHL 4 10 tPLH 2 0 -25 0 25 50 75 Ambient temperature Ta (C) S/Nq (RMS Signal/RMS Noise) vs. Clock frequency 100 0 -25 0 25 50 75 Ambient temperature Ta (C) S/Nq (RMS Signal/RMS Noise) vs. Analog input frequency 100 50 50 40 Ta = +70C Ta = +25C Ta = 0C 20 VCC = 5.00 V fin = 4.0 MHZ 10 S/Nq (dB) 40 30 S/Nq (dB) 30 20 VCC = 5.00 V fCLK = 20 MHz Ta = +25C 10 0 10 20 30 40 50 Clock frequency (MHz) 60 0 0 2 4 6 8 10 Analog input frequency (MHz) 11 MB40568 s EQUIVALENT CIRCUIT 1. Analog Input Equivalent Circuit VCCA VINA VCCA VD VINA CINA IBIAS RINA x 255 CIRCUITS A.GND A.GND VRB CINA : Non-linear Emitter-Follower Junction Capacitance RINA : Linear Resistance Model for Input Current Transition by Comparator Switching Infinite value for VINA < VRB or when CLK + High VRB : Voltage at VRB terminal. IBIAS : Constant Input Bias Current VD : The base-collector junction diode of emitter-follower transistor 2. Equivalent Circuit of Clamp Circuit Block VCCA 2 mA 0.6 x VCC + 200 mV + VBE VINC 850 k A.GND VOUTC - + VCLMP CCLMP 12 MB40568 3. Equivalent Circuit of Reference Circuit Block VCCA 20 k Buffer VRB pin IRB 30 k A.GND 4. Digital Input Equivalent Circuit VCCD 50 k 3.2 k 6.5 k 3.2 k 50 k Clock input VREF = 1.4 V D.GND 5. Load Circuit for Output Buffer To output pin CL Measurement point CL = 15 pF D.GND Note: CL = 15 pF including scope and jig capacitance 13 MB40568 s LINEARITY ERROR 1. Ideal Conversion Characteristics STEP 255 254 253 * * * 129 128 127 * * * 2 1 0 OUTPUT CODE 11111111 11111110 11111101 * * * 10000001 10000000 01111111 * * * 00000010 00000001 00000000 VZT 3.006 V V INA VFT 4.996 V The values for VZT and VFT are typical values under conditions that VCCA = VCCD = 5.000 V and VRB = 3.000 V. 14 MB40568 2. Actual Conversion Characteristics STEP 255 254 253 * * * 129 128 127 * * * 2 1 0 OUTPUT CODE 11111111 11111110 11111101 * * * 10000001 10000000 01111111 * * * 00000010 00000001 00000000 LE1 VZT VINA VFT LEn max = Linearity error FS LE2 LE128 LE127 LE129 LE253 15 MB40568 s CLAMP CIRCUIT OPERATION The MB40568's internal clamp circuit is a peak-detection type circuit, which clamps compound synchronized signals using the lowest sync point as clamp voltage (VCLMP) (see illustration below). The clamp voltage is set at 0.6 x VCC + 0.2 V (typical). If the clamp circuit is not used, the signal pins should be handled as follows: Pin name VINC VOUTC VCLMP * Clamp Circuit Description Connect to GND Leave open Leave open VCCA VCCA 2 mA Video signal VINC 15 A.GND VOUTC - + VCLMP 17 16 3.2 V Bias circuit CCLMP VINA 18 A/D converter (Pin No.: SK-DIP22P) Signal level at VINC pin Signal level at VINA pin VCCA = 5.0 V A.GND VCLMP 3.2 V VRB 3.0 V 16 MB40568 s TYPICAL CONNECTION EXAMPLES 1. On-Chip Input PNP Transistor Utilized +5 V +5 V VCCA VCCD Video signal input 15 VINC 16 VOUTC 1F - + 17 VCLMP MB40568 18 VINA A.GND D.GND (Pin No.: SK-DIP22P) 17 MB40568 2. Input PNP Transistor of Clamp Circuit is Put Externally +5 V +9 V External circuit VCCA 15 VINC 16 VOUTC 2.2 k 17 VCLMP MB40568 -+ 1 F Video signal input 2SA933 18 VINA +5 V VCCD A.GND D.GND (Pin No.: SK-DIP22P) 18 MB40568 s ORDERING INFORMATION Part number MB40568P-SK MB40568PF Package 20 pin Plastic SK-DIP (DIP-20P-M04) 24 pin Plastic SOP (FPT-24P-M02) Remarks 19 MB40568 s PACKAGE DIMENSIONS 20-pin Plastic SK-DIP (DIP-22P-M04) 27.18 -0.30 1.070 +.008 -.012 +0.20 INDEX-1 INDEX-2 6.600.25 (.260.010) 4.36(.172)MAX 0.51(.020)MIN 0.250.05 (.010.002) 0.460.08 (.018.003) +0.50 +.020 -0 +0.50 3.00(.118)MIN 0.86 -0 .034 1.27(.050) MAX 1.27 -0 .050 2.54(.100) TYP +.020 -0 7.62(.300) TYP 15MAX C 1994 FUJITSU LIMITED D22008S-4C-3 Dimensions in mm (inches) (Continued) 20 MB40568 (Continued) 24-pin Plastic SOP (FPT-24P-M02) 15.24 -0.20 .600 -.008 +0.25 +.010 2.80(.110)MAX 0.05(.002)MIN (STAND OFF) 7.600.30 10.200.40 (.299.012) (.402.016) 1 PIN INDEX 9.200.30 (.362.012) 1.27(.050)TYP 0.450.10 (.018.004) O0.13(.005) M 0.15 -0.02 +.002 .006 -.001 +0.05 0.500.20(.020.008) Details of "A" part 0.20(.008) 0.10(.004) "A" 0.60(.024) 0.18(.007)MAX 0.68(.027)MAX 13.97(.550)REF C 1994 FUJITSU LIMITED F24008S-4C-4 Dimensions in mm (inches) 21 MB40568 MEMO 22 MB40568 MEMO 23 MB40568 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. F9702 (c) FUJITSU LIMITED Printed in Japan 24 *DS04-28203 |
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